首页 > Synopsys 新思科技2022校招开始啦
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Kristen1122
编辑于 2021-08-14 12:33
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Synopsys 新思科技2022校招开始啦

各种师弟师妹,synopsys 2022届校招开始啦!

主要岗位有:

1.ASIC Design Engineer-数字设计工程师

Requirements:

Master degree in microelectronics, electronic engineering, communication or related fields;

微电子、电子工程、通信或相关专业研究生;

Good theoretical and practical understanding of digital signal processing and data recovery
circuits is required

深入理解ASIC/IP设计流程

Familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is a plus

熟悉Verilog和VCS。熟悉后端合成工具DC/PT

Good RTL debug capability;

良好的RTL调试能力

Work with verification team to debug and fix RTL issues;

与验证团队一起调试和修复RTL问题;

Scripting experience in Shell, Perl, Python and TCL is a plus

有Shell, Perl, Python和TCL脚本经验者优先

The related products are Interface controller, High Speed DDR PHY, Static memory,Processor etc.

从事的相关产品是接口控制器 (Interface controller) / 高速DDR PHY /静态存储器/处理器 (Processor) 等


2.ASIC Verification Engineer-数字验证工程师

Requirements:

Master degree in microelectronics, electronic engineering, communication or
related fields;  

微电子、电子工程、通信或相关专业研究生;

Knowledge in ASIC RTL design and verification at the chip level and block level; 

具有芯片级和模块级ASIC RTL设计和验证知识;

Strong Verilog, Verilog, UVM, PERL, and TCL
skills; 

熟悉Verilog,system Verilog, UVM, PERL和TCL技能

Knowledge in silicon debugging

了解芯片测试功能

Demonstrates good communication skills in both Mandarin and English

良好的沟通能力

Demonstrates good analysis and problem-solving skills

良好的分析和解决问题的能力

Knowledge of high speed interface protocols is a plus

具备高速接口协议知识优先

Working as part of a highly experienced IP design team, the candidate will be involved in designing and maintaining current and next generation, related products are Interface Controller/High-speed DDR PHY /Serdes/Static Memory/Processor using advanced design process (such as 5nm/7nm/10nm), etc;

作为经验丰富的IP设计团队的一员,你将将参与当前和下一代产品的设计和维护,相关产品为接口控制器/高速DDR PHY /Serdes/静态内存/处理器,使用先进的设计流程(如5nm/7nm/10nm)等;


3..A&MS Circuit Design Engineer模拟混合信号设计工程师

Job Description:

· Involved in analog design and mixed signal IP design;

参与模拟设计和混合信号IP设计;

· Incorporate test, debug and tuning controls;

整合测试、调试和调优控制;

· Work with a cross functional design team of analog and digital designers from a wide variety of backgrounds;

与来自不同部门的模拟和数字设计工程师的跨地区设计团队合作;

· Design innovative analog and mixed-signal integrated circuits based on leading edge technology (like 7nm/10nm)

基于前沿技术(如7nm/10nm)设计创新模拟和混合信号集成电路;

Requirements:

· Graduates in 2022, with degree in Microelectronics, Telecommunication, automatic control, electromechanical and electronics related fields;

2022年毕业,具备电子工程、电子 、微电子 、集成电路相关联专业本科以上学历;

· Have digital circuit design, analog circuit design and related learning experience or working experience;

具有信号与系统、数字/模拟电路、半导体物理、数字/模拟集成电路设计等相关专业课程基础或实践经验;

· Experience with tools for schematic entry, IC layout and SPICE simulation;

熟悉原理图输入、IC布局和SPICE仿真工具;

· Experience with TCL, Perl, C, python, MATLAB, or other scripting languages;

熟悉TCL,Perl,C,Python,MATLAB或其他脚本语言;

· Language proficiency over CET-4 and have good listening, writing and reading ability;

英文通过四级,有一定听说写能力;

· Good team player, quick learner and skillful communication.

良好的合作,学习能力和沟通能力。


4.ASIC/Layout Design Engineer – 版图设计工程师

Job Description:

Involve related to analog layout design and mixed signal IP layout design;

参与相关模拟版图设计和混合信号IP布局设计;

 To complete layout with custom design layout with advanced process node (Like 7nm/10nm) according to schematic, verify layout design with DRC/LVS deck;

根据原理图完成具有先进工艺节点(如7nm/10nm)的定制布局设计,用DRC/LVS平台验证布局设计;

Finish release projects on schedule and back up documents with working flow;

按时完成发布项目,按照工作流程备份文档;

Work with a cross functional layout design team from a wide variety of backgrounds;

与来自不同部门的模拟和数字设计工程师的跨地区设计团队合作;

To check released database quality with release engineers.

与设计工程师一起检查发布数据库的质量。

Requirement:

Graduates in 2022, majored in Microelectronics, Electronic Engineering and Electronic related fields, and know the CMOS process;

本科及以上学历 (微电子,电子信息,或者自动化专业优先考虑)

Be familiar with EDA tools 

熟悉EDA工具

Language proficiency over CET-4 and listening, writing and reading can meet basic daily working requirements;

英语四级以上,听、写、读能满足基本的日常工作要求;

Good team player and skillful communication.

良好的合作和沟通能力

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

以上岗位工作地点均在武汉,需要内推可以投简历至yuxin@ synopsys .com

即使不是微电子专业,有从事硬件电路板板级设计/fpga/等电子通信类专业也可进入

本人硕士阶段所做的是板级电路,会fpga然后找工作转入了ic行业,相比于传统硬件,ic行业岗位更多,薪资更高。欢迎各位师弟师妹砸简历。

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