Synopsys IP 职位售前售后热招中~
邮箱:limin@synopsys.com
社招岗位：北京/上海/深圳/
1. IP售前职位：
Interface IP Application Engineer_售前
Location: 北京/上海/深圳/
Job Description and Requirements
A presales AE (Application Engineer) is responsible for providing technical support for Synopsys' DesignWare Intellectual Property (DW IP) in presales stage within China with primary focus on Northern China region.
A presales AE’s responsibilities include:
1) Discussing with customer on their application and SoC design, Capturing and understanding their design requirements for Interface IP, Preparing IP technical solution with BU R&D to meet the requirements, Co-working with customer to update chip microarchitecture based on IP characteristics
2) Studying high speed interface protocol update, joining IP product update training and technical conference, and deepening expertise on Interface IP by systematic learning and hands-on IP practice as configuration, synthesis and verification
3) Working with sales teams to manage IP activities in the region to achieve a high customer satisfaction and for building strong customer relationships
4) Providing direct technical support and assistance if needed to enable customers to use DW IP successfully
5) Managing DW IP technical support requirements and needs for existing or prospective customers. This role requires AE to work and coordinate across business units and with other product line teams to provide high quality support for customers.
6) Providing technical guidance and support to sales team during calls, meetings, and marketing events.
Requirements:
Qualified applicants should have a BSEE, MSEE preferred, at least 5+ years relevant experience in ASIC/FPGA designs. Exposure to IP-based SOC design and real tape-out experience are highly desired.
Design, integration or verification experience with one or more high speed interface, such as Ethernet, USB, DP, DDR, HBM2e/2, PCIe, CCIX, MIPI, HDMI, Mobile Storage and Multi-protocol Serdes is required.
An understanding of system design and logic design using an HDL language, synthesis, simulation and verification CAD tools is essential. Hands on experience with DC or equivalent is preferred.
Customer interaction related experience is preferred.
Technical or domain knowledge on 5G IoT, 5G mobile, AI and Automotive is a plus.
The ability to conduct technical meetings, presentations, product demonstrations, and training to customers and the sales team is required.
Good written and verbal communication skills in both Mandarin and English are required.
A presales AE (Application Engineer) is responsible for providing technical support for Synopsys' DesignWare Intellectual Property (DW IP) in presales stage within China with primary focus on Northern China region.
A presales AE’s responsibilities include:
1) Discussing with customer on their application and SoC design, Capturing and understanding their design requirements for Interface IP, Preparing IP technical solution with BU R&D to meet the requirements, Co-working with customer to update chip microarchitecture based on IP characteristics
2) Studying high speed interface protocol update, joining IP product update training and technical conference, and deepening expertise on Interface IP by systematic learning and hands-on IP practice as configuration, synthesis and verification
3) Working with sales teams to manage IP activities in the region to achieve a high customer satisfaction and for building strong customer relationships
4) Providing direct technical support and assistance if needed to enable customers to use DW IP successfully
5) Managing DW IP technical support requirements and needs for existing or prospective customers. This role requires AE to work and coordinate across business units and with other product line teams to provide high quality support for customers.
6) Providing technical guidance and support to sales team during calls, meetings, and marketing events.
Requirements:
Qualified applicants should have a BSEE, MSEE preferred, at least 5+ years relevant experience in ASIC/FPGA designs. Exposure to IP-based SOC design and real tape-out experience are highly desired.
Design, integration or verification experience with one or more high speed interface, such as Ethernet, USB, DP, DDR, HBM2e/2, PCIe, CCIX, MIPI, HDMI, Mobile Storage and Multi-protocol Serdes is required.
An understanding of system design and logic design using an HDL language, synthesis, simulation and verification CAD tools is essential. Hands on experience with DC or equivalent is preferred.
Customer interaction related experience is preferred.
Technical or domain knowledge on 5G IoT, 5G mobile, AI and Automotive is a plus.
The ability to conduct technical meetings, presentations, product demonstrations, and training to customers and the sales team is required.
Good written and verbal communication skills in both Mandarin and English are required.
2. IP售后职位：
Job Title： Interface IP Application Engineer (DDR/HBM/Serdes/MIPI/eMMC)
Location： 上海/北京/深圳
Description
This position requires a highly motivated and experienced individual to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products. IIP include PCIe4/5, USB3/3.1/3.2/4, DDR/LPDDR4/4x/5, HDMI2.1, MIPI DPHY/MPHY and high speed SerDes up to 112G.
The position offers opportunities to work on Synopsys IIP and the latest industry specifications/applications on various hot market segments. The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges, perform integration reviews at key milestones and support silicon/system bring-up. Some travels will be required.
Responsibilities Include
Understand IIP applications on customer specific SoC and systems
Keep abreast of the latest ASIC/SoC design flows and EDA tools
Provide expert advice and support to configure and resolve IIP integration challenges including simulation, synthesis, floorplan, STA, DFT, silicon bring-up, etc.
Provide integration training to customers and conduct reviews on their major SoC milestones
Provide feedback to Synopsys R&D for continuous IIP product improvements
Participate in IIP R&D design reviews to align development with future customer needs
Location： 上海/北京/深圳
Description
This position requires a highly motivated and experienced individual to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products. IIP include PCIe4/5, USB3/3.1/3.2/4, DDR/LPDDR4/4x/5, HDMI2.1, MIPI DPHY/MPHY and high speed SerDes up to 112G.
The position offers opportunities to work on Synopsys IIP and the latest industry specifications/applications on various hot market segments. The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges, perform integration reviews at key milestones and support silicon/system bring-up. Some travels will be required.
Responsibilities Include
Understand IIP applications on customer specific SoC and systems
Keep abreast of the latest ASIC/SoC design flows and EDA tools
Provide expert advice and support to configure and resolve IIP integration challenges including simulation, synthesis, floorplan, STA, DFT, silicon bring-up, etc.
Provide integration training to customers and conduct reviews on their major SoC milestones
Provide feedback to Synopsys R&D for continuous IIP product improvements
Participate in IIP R&D design reviews to align development with future customer needs
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